In recent years, the degree of integration in semiconductor devices has advanced. Copper is sometimes used in semiconductor devices as an interconnect material instead of tungsten or an aluminum alloy. Copper has high reliability and low specific resistance. In comparison to pure copper interconnects, copper alloy interconnects have excellent reliability and corrosion resistance, in spite of their relatively high resistivity. However, copper is used instead of tungsten and aluminum alloys because Tungsten and aluminum alloys exhibit high resistivity and low reliability due to EM (Electro Migration) and SM (Stress Migration).
EM is a glitch caused by an increase of current density in metal interconnects. The increase in current density results from high speed operations and the miniaturized width of the interconnects.
SM is a creep facture mode caused by mechanical stress on an interconnect. The difference in the thermal expansion factors between a metal interconnect and an insulating layer covering the metal interconnect for protection is typically the cause of this mechanical stress.
The dual damascene process for inlaying metals on the interconnect line is prevalently performed in later stages. This process was developed to overcome the inefficiency of a copper etching process. In solving problems arising from the different structure and the complete change of equipment, the copper dual damascene process has been proven to be cost-effective and process friendly.
FIG. 1a through FIG. 1d are cross-sectional views which schematically illustrate a prior art method of fabricating a copper interconnect.
Referring to FIG. 1a, an insulating layer 10 is deposited on a substrate (not shown) including predetermined devices. A trench and a via opening are formed on the insulating layer 10 through a dual damascene process. A barrier layer 11 is then deposited over the trench and the via opening. The trench and the via opening are then filled with copper 12 through an ECP (Electro Chemical Plating) process and a CMP (Chemical Mechanical Polishing) process to form the bottom copper interconnect.
Referring to FIG. 1b, a capping layer 13 is made on the copper interconnect by depositing a SiN layer with a thickness of about 700 Å over the substrate and the bottom copper interconnect.
Referring to FIG. 1c, an interlayer insulating layer 14 is deposited on top of the capping layer 13 to insulate the copper interconnect.
Referring to FIG. 1d, a via hole 15 is made by etching the interlayer insulating layer 14 with a photoresist mask. The via hole 15 is then filled with a conducting material, thereby forming a via (i.e., a plug or interlayer connector) which connects the bottom interconnect with an upper interconnect.
The above-mentioned methods for fabricating a copper interconnect have several problems.
First, once oxidized regions are formed on the surface of copper, a gap may be generated between the SiN layer and the surface of the copper due to poor adhesion. A short between interconnects may occur due to copper diffusion into the gap.
Second, when the via is formed to connect an upper interconnect with a bottom interconnect, if the capping layer is not properly opened, a connection may not be formed between the upper interconnect and the bottom interconnect.
Finally, the high dielectric constant of the SiN layer may cause an increase of the overall dielectric constant between the bottom interconnect and the upper interconnect.
Somekh, U.S. Pat. No. 6,291,334 describes a method of forming an etching stop layer for a dual damascene process.
Yu et al., U.S. Pat. No. 6,100,161, describe a method of fabricating a raised source/drain transistor.